As integrated circuit (IC) process technology advances to higher densities, the feature size of a transistor is reduced enabling low-voltage high speed operation and high density layout. Another result of the reduced feature size is to also reduce the transistor's gate oxide voltage tolerance. Some conventional input/output (I/O) standards require an IC to interface with external voltages that are higher than the internal voltages used within the IC. Thus, it may be necessary to interface low-voltage transistors to high-voltage systems in some IC design. This is an important challenge in I/O design.
FIG. 1 shows a first conventional level shifter comprising a half latch made up of thick oxide transistors, which are transistors having relatively thick gate oxide. On the other hand, thin oxide transistors are transistors having relatively thin gate oxide. In general, thick oxide transistors are slower than thin oxide transistors. In general, the thickness of a gate of a transistor depends on the fabrication process, and hence, the defining dimensions for thick oxide transistors and thin oxide transistors also depend on the fabrication process. Thick oxide transistors are used in the conventional level shifter in FIG. 1, as thin oxide transistors may not tolerate high voltages across their gate to source terminals (Vgs) and across their gate to drain terminals (Vgd) due to higher electric fields across the oxide for the same Vgs or Vgd as compared to a thicker oxide. The electric field across the oxide is proportional to Vgs/tox, where tox is the thickness of the oxide, and when the electric field exceeds a critical value, the oxide breaks down and loses its insulating character. This makes thin oxide transistors more susceptible to breakdown at higher Vgs and Vgd voltages. Referring back to FIG. 1, the gates of transistors MN0 and MN1 are driven by low voltage differential input signals from the interior of the chip on which the level shifter is implemented. The low voltage differential input signals' maximum value is a level shifted high voltage value, VLV. The drains are connected via the p-type metal oxide semiconductor (PMOS) devices MP0 and MP1 to VLV.
The conventional level shifter 100 operates in the following manner. When input signal In is high, the gate of MP1 is pulled low and the output node 190 is pulled high to the value VHV. When Inb goes high and In goes low, MN1 pulls down the output node 190 and also turns on MP0, which in turn shuts off MP1. The speed of the level shifter 100 is limited by at least two factors. The first factor is the use of the slow thick oxide devices driven by low voltage signals, and the second factor is the contention between the N and P devices. MN1 and MN0 have to fight MP0 and MP1 during the falling and rising transitions of the output node 190. In the level shifter 100, the rise delay of the output is the critical path as it requires the discharge of the gate of MP1 and the charging of the output node 190.
A second conventional level shifter is shown in FIG. 2. The level shifter 200 is a modification of the level shifter 100 in FIG. 1, in which the contention between the pull-up PMOS and the pull-down n-type metal oxide semiconductor (NMOS) transistors is eliminated. The second conventional level shifter 200 comprises an inverter 11, a weak PMOS keeper transistor MP3, a PMOS transistor MP4, and a NMOS transistor MN2, all of which are thick oxide transistors.
Analyzing the rising transition of the output node 290, it is assumed that MN2 is turned on initially. When signal In rises, the signal In pulls down the gate of MP1, which in turn starts to charge up the output node 290. When the voltage at the output node 290 rises above the trip point of inverter I1, the output Y of inverter I1 goes low to turn off MN2 and to turn on MP4 and MP3. In a third step, this in turn turns off MP1, and the pull up of the output node 290 is completed by MP3. So, as long as the output node 290 voltage is above the trip point of the next stage when MP1 switches off, there is little or no penalty in the rise delay.
Analyzing the falling transition of the output node 290 when Inb goes high, MN1 in the level shifter 200 has to fight the weak keeper transistor MP3 instead of the strong pull-up transistor MP1, so the fall delay of the output node 290 may be improved by this change.
In a third conventional solution, a corresponding change may be made at node X of the level shifter 200 to improve the rising transition of the output node 290. However, there may be a penalty on doing so because there are two thick oxide NMOS transistors N10 and MN2 in the pull-down path of the gate of MP1.